This application claims the benefit of Japanese Application No. 2001-141186 filed May 11, 2001.
The present invention relates to a fast A/D (Analog to Digital) conversion signal processor, an RF (Radio Frequency) receiver circuit, a digital receiver front end circuit, an MRI (Magnetic Resonance Imaging) apparatus, and a fast A/D conversion device. More particularly, the invention relates to a fast A/D conversion signal processor which, even in the presence of discordance in terms of timing between the output of digital data from a fast A/D converter and the clock signal for a digital signal process used by a digital signal process section, can absorb the discordance and deliver the digital data from the fast A/D converter to the digital signal process section properly, an RF receiver circuit and digital receiver front end circuit which can be used for the fast A/D conversion signal processor, an MRI apparatus which uses the fast A/D conversion signal processor, and a fast A/D conversion device which can be used for the fast A/D conversion signal processor.
In recent years, digitization of signal processing is advancing also in MRI apparatus. Specifically, in an advanced scheme, an NMR signal received by a receiving coil is converted with a fast A/D converter into digital data, with resulting digital-data being delivered to a digital signal process section, which implements a digital signal processing (e.g., digital filtering) for the digital data, with resulting data being delivered to a computer, which implements an image recomposing process or the like.
In delivering digital data released by a fast A/D converter to a digital signal process section, there emerges the discordance in terms of timing between the output of digital data from the fast A/D converter and the clock signal for a digital signal process used by the digital signal process section.
This timing discordance is the natural consequence in case the clock signal for the fast A/D converter and the clock signal for the digital signal process are produced independently of each other, and it also emerges when one clock signal is used distributively as both clock signals. Conceivable causes are that the clock signal circuit for the fast A/D converter uses an RF pulse transformer for generating differential RF clock signals which are needed by the fast A/D converter, and that there is the disparity in the timing of output of digital data from the fast A/D converter among circuit devices, and that there is a difference between the delay time of a digital data transfer system and the delay time of a clock signal transfer system.
Hence, in the presence of the above-mentioned discordance of timing, it is problematic in that the fast A/D converter can possibly fail to deliver digital data to the digital signal process section properly.
Therefore, a first object of the present invention is to provide a fast A/D conversion signal processor which, even in the presence of discordance in terms of timing between the output of digital data from a fast A/D converter and the clock signal for a digital signal process used by a digital signal process section, can absorb the discordance and deliver the digital data from the fast A/D converter to the digital signal process section properly.
A second object of the present invention is to provide an RF receiver circuit and digital receiver front end circuit which can be used for the fast A/D conversion signal processor.
A third object of the present invention is to provide an MRI apparatus which uses the fast A/D conversion signal processor.
A fourth object of the present invention is to provide a fast A/D conversion device which can be used for the fast A/D conversion signal processor.
At a first viewpoint, the present invention resides in a fast A/D conversion signal processor which is characterized by comprising a fast A/D converter which converts an input analog signal into digital data at an operation speed of 20 MHz or higher, a digital signal process section which implements a digital signal processing for the digital data, and data memory means which stores the digital data released by the fast A/D converter in synchronism with a data ready signal provided by the fast A/D converter and reads out the stored digital data and delivers to the digital signal process section in synchronism with a clock signal for a digital signal process used by the digital signal process section.
In the fast A/D conversion signal processor of the first viewpoint, digital data is stored in the data memory means at the timing of output of the digital data from the fast A/D converter (at the timing which is based on the data ready signal). Digital data is read out of the data memory means and delivered to the digital signal process section at the operation timing of the digital signal process section (at the timing which is based on the clock signal for the digital signal process). In consequence, even in the presence of discordance in terms of timing between the output of digital data from the fast A/D converter and the clock signal for the digital signal process used by the digital signal process section, the discordance is absorbed by the intervention of the data memory means and the digital data can be delivered from the fast A/D converter to the digital signal process section properly.
In the above-mentioned arrangement, the xe2x80x9cdata ready signalxe2x80x9d signifies a xe2x80x9csignal indicative of the output period of valid dataxe2x80x9d, and it may be called xe2x80x9cdata valid signalxe2x80x9d.
At a second viewpoint, the present invention resides in the fast A/D conversion signal processor of the foregoing arrangement, which is characterized in that the data memory means includes a dual-clock-synchronous FIFO (First-In-First-Out), a write control circuit which responds to a start signal indicative of the commencement of storing to store the digital data released by the fast A/D converter into the dual-clock-synchronous FIFO in synchronism with the data ready signal, and a readout control circuit which responds to an empty signal provided by the dual-clock-synchronous FIFO to read the digital data out of the dual-clock-synchronous FIFO in synchronism with the clock signal for the digital signal process.
In the fast A/D conversion signal processor of the second viewpoint, it is possible to write the digital data released by the fast A/D converter into the dual-clock-synchronous FIFO based on the input of the start signal from the outside. Digital data is read out of the dual-clock-synchronous FIFO in response to the empty signal which is produced when the digital data is written into the dual-clock-synchronous FIFO, and consequently the digital data can be delivered from the fast A/D converter to the digital signal process section properly.
At a third viewpoint, the present invention resides in the fast A/D conversion signal processor of the foregoing arrangement, which is characterized in that the readout control circuit produces and releases a sync ready signal for indicating to the outside that digital data is amid the readout of the dual-clock-synchronous FIFO.
In the fast A/D conversion signal processor of the third viewpoint, it is possible to know the output timing of digital data from the dual-clock-synchronous FIFO by monitoring the sync ready signal.
At a fourth viewpoint, the present invention resides in the fast A/D conversion signal processor of the foregoing arrangement, which is characterized by comprising a high-stability crystal oscillator, an RF multiplying circuit which produces an RF clock signal having a frequency that is a multiple of the frequency of the output signal of the high-stability crystal oscillator, and an RF pulse transformer which produces differential RF clock signals to be used by the fast A/D converter from the RF clock signal.
With the fast A/D conversion signal processor of the fourth viewpoint, it is possible to produce properly the differential RF clock signals needed by the fast A/D converter.
At a fifth viewpoint, the present invention resides in the fast A/D conversion signal processor of the foregoing arrangement, which is characterized by comprising a separation RF pulse transformer which produced from the RF clock signal a separated clock signal which is separated electrically from the RF clock signal, and a comparator which produces the clock signal for the digital signal process from the separated clock signal.
In the fast A/D conversion signal processor of the fifth viewpoint, it is possible to produce from one clock signal the differential RF clock signals needed by the fast A/D converter and the clock signal for the digital signal process. In addition, using the separation RF pulse transformer can prevent the entry of noises from one of the analog RF circuit and digital circuit into another by way of the clock transfer system.
At a sixth viewpoint, the present invention resides in an MRI apparatus which is characterized by including the fast A/D conversion signal processor of the foregoing arrangement, and being adapted to process with the fast A/D conversion signal processor an NMR signal which is received by a receiving coil.
With the MRI apparatus of the sixth viewpoint, it is possible to advance properly the digitization of process of the received signal of MRI apparatus.
At a seventh viewpoint, the present invention resides in an RF receiver circuit which is characterized by comprising a fast A/D converter which converts an input analog signal into digital data at an operation speed of 20 MHz or higher, a high-stability crystal oscillator, an RF multiplying circuit which produces an RF clock signal having a frequency that is a multiple of the frequency of the output signal of the high-stability crystal oscillator, an RF pulse transformer which produces differential RF clock signals to be used by the fast A/D converter from the RF clock signal, a clock driver which delivers to the outside a data ready signal produced by the fast A/D converter, a separation RF pulse transformer which produced from the RF clock signal a separated clock signal which is separated electrically from the RF clock signal, a comparator which produces a clock signal for a digital signal process from the separated clock signal, and a latch which holds and releases in synchronism with the data ready signal the digital data released by the fast A/D converter.
By using the RF receiver circuit of the seventh viewpoint, it is possible to advance properly the digitization of process of the received signal of MRI apparatus.
At an eighth viewpoint, the present invention resides in a digital receiver front end circuit which is characterized by comprising a first clock buffer which produces a data ready signal from a first input clock signal, a second clock buffer which produces from a second input clock signal and releases also to the outside a clock signal for a digital signal process, a latch which holds and releases input digital data in synchronism with the data ready signal, and data memory means which stores the digital data released by the latch in synchronism with the data ready signal and reads out and releases the stored digital data in synchronism with the clock signal for the digital signal process.
By using the digital receiver front end circuit of the eighth viewpoint, it is possible to advance properly the digitization of process of the received signal of MRI apparatus.
At a ninth viewpoint, the present invention resides in the digital receiver front end circuit of the foregoing arrangement, which is characterized in that the data memory means includes a dual-clock-synchronous FIFO, a write control circuit which responds to a start signal indicative of the commencement of storing to store the input digital data into the dual-clock-synchronous FIFO in synchronism with the data ready signal, and a readout control circuit which responds to an empty signal provided by the dual-clock-synchronous FIFO to read the digital data out of the dual-clock-synchronous FIFO in synchronism with the clock signal for the digital signal process.
By using the digital receiver front end circuit of the ninth viewpoint, it is possible to advance properly the digitization of process of the received signal of MRI apparatus.
At a tenth viewpoint, the present invention resides in the digital receiver front end circuit of the foregoing arrangement, which is characterized in that the readout control circuit produces and releases a sync ready signal for indicating to the outside that digital data is amid the readout of the dual-clock-synchronous FIFO.
By using the digital receiver front end circuit of the tenth viewpoint, it is possible to advance properly the digitization of process of the received signal of MRI apparatus.
At an eleventh viewpoint, the present invention resides in an MRI apparatus which is characterized by comprising the RF receiver circuit of the foregoing arrangement, the digital receiver front end circuit of the foregoing arrangement, and a digital signal process section, and characterized in that an NMR signal received by a receiving coil is put as input analog signal into the RF receiver circuit, the digital data released by the latch of the RF receiver circuit is put as input digital data into the digital receiver front end circuit, the data ready signal provided by the clock driver of the RF receiver circuit is put as a first input clock signal into the digital receiver front end circuit, the clock signal for the digital signal process provided by the comparator of the RF receiver circuit is put as a second input clock signal into the digital receiver front end circuit, and the digital data released by the dual-clock-synchronous FIFO of the digital receiver front end circuit and the clock signal for the digital signal process provided by the second clock buffer are put into the digital signal process section.
With the digital receiver front end circuit of the eleventh viewpoint, it is possible to advance properly the digitization of process of the received signal.
At a twelfth viewpoint, the present invention resides in an MRI apparatus which is characterized by comprising the RF receiver circuit of the foregoing arrangement, the digital receiver front end circuit of the foregoing arrangement, a digital signal process section, and a control logic section which produces the start signal and puts into the digital receiver front end circuit in response to a pulse sequence, and characterized in that an NMR signal received by a receiving coil is put as input analog signal into the RF receiver circuit, the digital data released by the latch of the RF receiver circuit is put as input digital data into the digital receiver front end circuit, the data ready signal provided by the clock driver of the RF receiver circuit is put as a first input clock signal into the digital receiver front end circuit, the clock signal for the digital signal process provided by the comparator of the RF receiver circuit is put as a second input clock signal into the digital receiver front end circuit, the digital data released by the dual-clock-synchronous FIFO of the digital receiver front end circuit and the clock signal for the digital signal process provided by the second clock buffer are put into the digital signal process section, and the clock signal for the digital signal process provided by the second clock buffer of the digital receiver front end circuit is put into the control logic section.
With the digital receiver front end circuit of the twelfth viewpoint, it is possible to advance properly the digitization of process of the received signal.
At a thirteenth viewpoint, the present invention resides in an MRI apparatus which is characterized by comprising the RF receiver circuit of the foregoing arrangement, the digital receiver front end circuit of the foregoing arrangement, a digital signal process section, and a control logic section which produces the start signal and puts into the digital receiver front end circuit in response to a pulse sequence, and characterized in that an NMR signal received by a receiving coil is put as input analog signal into the RF receiver circuit, the digital data released by the latch of the RF receiver circuit is put as input digital data into the digital receiver front end circuit, the data ready signal provided by the clock driver of the RF receiver circuit is put as a first input clock signal into the digital receiver front end circuit, the clock signal for the digital signal process provided by the comparator of the RF receiver circuit is put as a second input clock signal into the digital receiver front end circuit, the digital data released by the dual-clock-synchronous FIFO of the digital receiver front end circuit and the clock signal for the digital signal process provided by the second clock buffer are put into the digital, signal process section, and the sync ready signal provided by the readout control circuit of the digital receiver front end circuit and the clock signal for the digital signal process provided by the second clock buffer are put into the control logic section.
With the digital receiver front end circuit of the thirteenth viewpoint, it is possible to advance properly the digitization of process of the received signal.
At a fourteenth viewpoint, the present invention resides in a fast A/D conversion device which is characterized by comprising a fast A/D converter which converts an input analog signal into digital data at an operation speed of 20 MHz or higher, and data memory means which stores the digital data released by the fast A/D converter in synchronism with a data ready signal provided by the fast A/D converter and reads out the stored digital data in synchronism with a readout clock signal provided from the outside.
In the fast A/D conversion device of the fourteenth viewpoint, digital data is stored in the data memory means at the timing of output of the digital data from the fast A/D converter. Digital data is read out of the data memory means in synchronism with a readout clock signal provided from the outside. In consequence, even in the presence of discordance in terms of timing between the output of digital data from the fast A/D converter and the clock signal for a digital signal process used by an external circuit which processes the digital data, it is possible to absorb the discordance.
At a fifteenth viewpoint, the present invention resides in the fast A/D conversion device of the foregoing arrangement, which is characterized in that the data memory means includes a dual-clock-synchronous FIFO, a write control circuit which responds to a start signal provided from the outside to store the digital data released by the fast A/D converter into the dual-clock-synchronous FIFO in synchronism with the data ready signal, and a readout control circuit which responds to an empty signal provided by the dual-clock-synchronous FIFO to read the digital data out of the dual-clock-synchronous FIFO in synchronism with the readout clock signal.
In the fast A/D conversion device of the fifteenth viewpoint, it is possible by providing the start signal from the outside to write the digital data released by the fast A/D converter into the dual-clock-synchronous FIFO. Digital data is read out of the dual-clock-synchronous FIFO in response to the empty signal which is produced at the time of writing of the digital data into the dual-clock-synchronous FIFO, and consequently it is possible to deliver properly the digital data from the fast A/D converter to an external circuit which processes the digital data.
At a sixteenth viewpoint, the present invention resides in the fast A/D conversion device of the foregoing arrangement, which is characterized in that the readout control circuit produces and releases a sync ready signal for indicating to the outside that digital data is amid the readout of the dual-clock-synchronous FIFO.
In the fast A/D conversion device of the sixteenth viewpoint, it is possible to know the output timing of digital data from the dual-clock-synchronous FIFO by monitoring the sync ready signal.
According to the fast A/D conversion signal processor of this invention, even in the presence of discordance in terms of timing between the output of digital data from the fast A/D converter and the clock signal for a digital signal process used by the digital signal process section, it becomes possible to absorb the discordance and deliver the digital data from the fast A/D converter to the digital signal process section properly.
According to the RF receiver circuit and digital receiver front end circuit of this invention, it is possible to arrange the fast A/D conversion signal processor properly.
According to the MRI apparatus of this invention, it becomes possible to attain the digitization of process of the received signal.
Further objects and advantages of the present invention will be apparent from the following description of the preferred embodiments of the invention as illustrated in the accompanying drawings.